tests/lvs: let the reference netlist decide which labels are pins, and the caller pick the gf180 MIM option - #112

Cell LVS on main fails on diff_pair, diff_pair_ibias and opamp, all with
the same shape: "extra top-level pin(s) in layout" for SUB and VTAIL.

A pin label is not a property of a cell, it is a property of how the cell is
used. VTAIL is a top-level pin of a standalone diff_pair and an internal net
inside diff_pair_ibias. Elementary cells emit labels so they can be LVS'd on
their own, and a parent that flattens them inherits those names.

Fixing that in the generator means every composite has to suppress its
children's labels at every level of the hierarchy. `with_pin_labels` does
this for diff_pair, but the parameter stops there: diff_pair_ibias does not
accept it and emits labels of its own, so opamp cannot suppress anything.
Each new composite is one more place that has to remember, and one that
forgets fails silently -- which is how these three got here.

The reference netlist already states which names are pins. Honour that when
staging inputs: drop labels whose text is not a port of the top `.subckt`.
No cell has to cooperate, it works at any depth and whether or not the
parent flattened, and it needs no ambient state -- relevant because `@cell`
keys its cache on arguments, so a context manager or env var can hand back a
stale component built under the opposite setting.

Only the staged copy is filtered; the GDS a cell ships keeps its labels, so
LEF and macro flows are unaffected. Matching is case-insensitive: generators
and schematics disagree on capitalisation in practice (`vdd` vs `Vdd`).

Dropping every label is reported as a warning rather than passed over: that
is not inheritance but a naming mismatch, and silently leaving the layout
with no pins would turn it into a confusing LVS failure downstream. With no
readable ports, nothing is dropped.

Measured on nine real cells, 5-12 labels over 49-4913 polygons: 0.1-1.0 ms
to filter, ~27 ms including the GDS round trip, against 1-8 s per cell of
LVS.

The repo has 14 tests under tests/ and no workflow executes any of them.

That matters more than it looks: the DRC and LVS workflows run the
gdsfactory backend (CPython 3.10, gdsfactory 7.7), so gdstk has no CI
coverage at all today, and conftest.py pins the test suite to gdstk. This
job is the first thing that exercises it.

It also gives pull requests a check they can currently fail. lvs.yml is
triggered by `workflow_run` off Cell DRC, which only fires on the default
branch: LVS has runs on main and none on any fork branch, so a PR that fixes
or breaks LVS cannot be seen either way until after it merges.

Deliberately not `pip install -e .`: install_requires pins gdsfactory<=7.7.0
and numpy<=1.24.0, which forces CPython 3.10 and pulls the whole layout
stack. None of it is needed -- verified in a clean venv with only pytest,
gdstk, numpy, pandas, pydantic and docopt: 19 passed in 7.2 s.

tests/test_cells_layout.py is left out. It builds every cell in both
backends, takes ~85 s, and carries five documented xfails, so green there
would mean "nothing changed" rather than "everything works". Cell-build
coverage deserves its own argument, and its own PR.

Listing the four files reproduces the problem this job exists to fix: a test
added later is not run until someone remembers to edit the workflow. ReaLLMASIC#100
adds tests/test_narrow_fets.py, which the explicit list would have silently
skipped.

Everything under tests/ now runs except test_cells_layout.py, which stays
out for the reason already documented above the step.

The runner hardcoded option A, so a cell drawing its MIM on option B
(met4/FuseTop/met5) extracted no capacitor at all and every MIM reported
as missing from the layout. The two options are mutually exclusive at
process level, so the deck can only be told one of them.

Adds --mim-option / $GF180_MIM_OPTION, defaulting to A as before, and
applies the option-A deck repair only when option A is selected -- the
deck's option B branch already connects all three plates.